Typical memory systems use either an asynchronous or synchronous clocking scheme to transmit data between the memory controller and the memory device. Synchronous clocking means that the memory device waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. Synchronous dynamic random access memory (SDRAM) is widely used since such devices typically support higher clock speeds than asynchronous memory devices.
Double data rate (DDR) SDRAM transfers data on both the rising and falling edges of the clock signal. Such memory devices use a lower clock frequency but require strict control of the timing of the electrical data and clock signals. The first version of such devices (DDR1) achieved nearly twice the bandwidth of a single data rate (SDR) SDRAM running at the same clock frequency. DDR2 and DDR3 SDRAM devices are subsequent improvements over DDR1 devices. Regardless of which type of DDR memory is used (DDR1/DDR2/DDR3), a physical interface (Phy) is coupled directly between the memory controller and the DDR SDRAM devices. The Phy interface generally includes circuitry for handling the timing requirements of the DDR SDRAM data strobes. Typical Phy interface implementations provide no mechanism to rapidly adjust memory performance level or demanded power.